Achronix Speedster22i User Macro Guide Uživatelský manuál stáhnout pdf (Strana 72)

Registers DFFEP

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 56

Table 2-12: Function Table

Inputs Output

pn ce d ck q



Verilog Instantiation Template

DFFEP #(.init(1’b1))

instance_name

(.q(user_out),

.d(user_din),

.pn(user_preset),

.ce(user_clock_enable),

.ck(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFEP_instance_name : DFFEP

generic map ( init => ‘1’)

port map (q => user_out,

d => user_din,

pn => user_preset,

ce => user_clock_enable,

ck => user_clock);

X0XXHold

01X 1

0 0

1 1

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 223 224

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Achronix Speedster22i User Macro Guide Uživatelský manuál Strana 72