Achronix Speedster22i User Macro Guide Uživatelský manuál stáhnout pdf (Strana 94)

Registers DFFNS

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 78

Table 2-44: Function Table

Inputs Output

sn d ckn q



when sr_assertion = “unclocked’

Table 2-45: unction Table

Inputs Output

sn d ckn q



when sr_assertion = “clocked’

Verilog Instantiation Template

DFFNS #(.init(1’b1))

instance_name

(.q(user_out),

.d(user_din),

.sn(user_set),

.ckn(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFNS_instance_name : DFFNS

generic map (

init => ‘1’)

port map (q => user_out,

d => user_din,

sn => user_set,

ckn => user_clock);

0X X 1

1X XHold

10 0

11 1

0X  1

XHold

10 0

11 1

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 223 224

Žádné komentáře

Achronix Speedster22i User Macro Guide Uživatelský manuál Strana 94