Achronix Speedster22i User Macro Guide Uživatelský manuál stáhnout pdf (Strana 65)

Speedster22i Macro Cell Library AchronixSemiconductorProprietary PAGE 49

Chapter 2 – Registers

Naming Convention

TheseMacrosarenamedbasedupontheircharacteristicsandbehavior.Ineachcase,thename

begins with DFF for D‐type Flip Flop. In addition to DFF each has one or more modifiers

whichindicatesit’suniqueproperties.

Themodifie

rsare:

E‐

Enable

N‐Negativ

elyClocked

R‐Reset(haspriorityov

erenable)

S‐Se

t(haspriorityoverenable)

C‐Clear(enabl

ehaspriority)

P‐Pre

set(enablehaspriority)

DFF

Positive Clock Edge D-Type Register

DFF

Figure 2-1: Logic Symbol

DFFisasi

ngleD‐typeregisterwithdatainput(d)andclock(ck)inputsanddata(q)output.

Thedataoutputissettothevalueonthedatainputuponthenextrisingedgeoftheclock.

Pins

Table 2-1: Pin Descriptions

Name Type Description

d Data input.

ck Positive-edge clock input.

Data output. T

he value present on the data input is transferred to the q out-

put upon the rising edge of the clock.

input

output

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 223 224

Žádné komentáře

Achronix Speedster22i User Macro Guide Uživatelský manuál Strana 65