Achronix Speedster22i User Macro Guide Uživatelský manuál stáhnout pdf (Strana 92)

Registers DFFNR

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 76

Table 2-40: Function Table

Inputs Output

rn d ckn q



when sr_assertion = “unclocked’

Table 2-41: Function Table

Inputs Output

rn d ckn q



when sr_assertion = “clocked’

Verilog Instantiation Template

DFFNR #(.init(1’b0))

instance_name

(.q(user_out),

.d(user_din),

.rn(user_reset),

.ckn(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFNR_instance_name : DFFNR

generic map (

init => ‘0’)

port map (q => user_out,

d => user_din,

rn => user_reset,

ckn => user_clock);

0X X 0

1X XHold

10 0

11 1

0X  0

XHold

10 0

11 1

1 2 ... 87 88 89 90 91 92 93 94 95 96 97 ... 223 224

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Achronix Speedster22i User Macro Guide Uživatelský manuál Strana 92