Achronix Speedster22i User Macro Guide Uživatelský manuál stáhnout pdf (Strana 99)

Speedster Macro Cell Library www.achronix.com PAGE 82

Chapter 3 – Logic Functions

MUX2

Two Input Multiplexer Gate

din0

MUX2

dout

din1

sel

Figure 3-1: Logic Symbol

MUX2 implements a tw

o‐input multiplexer gate that has each of  the twodata inputs (din0,

din1)connecteddirectlyto theoutputsofapairofLUT4blocksinanRLB.TheMUX2,when

combinedwithtwoLUT4s,canbeusedaseitheraLUT5,a4:1multiplexer,orafunctionofup

tonineinpu

ts.

Pins

Table 3-1: Pin Descriptions

Name Type Description

din0, din1 Data inputs.

sel Data Selectinput.

dout Data Output.

Table 3-2: Function Table

sel din0 din1 dout

X 0 0 0

X 1 1 1

Verilog Instantiation Template

MUX2 instance_name (.dout(user_out),

.sel(user_sel),

.din0(user_din0),

.din1(user_din1));

input

output

00X0

1X00

1X11

1 2 ... 94 95 96 97 98 99 100 101 102 103 104 ... 223 224

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Achronix Speedster22i User Macro Guide Uživatelský manuál Strana 99