Achronix Speedster22i HD1000 Development Kit User Guide Uživatelský manuál

UG034, July 1, 2014 1 ACX-KIT-HD1000-100G Development Kit User Guide UG034, July 1, 2014

10 UG034, July 1, 2014 Chapter 1 – ACX-KIT-HD1000-100G Overview In this chapter, you will learn the following about the ACX-KIT-HD1000-100G kit: AC

UG034, July 1, 2014 11 ACX-BRD-HD1000-100G Development Board Features FPGA  Achronix 22-nm, AC22IHD1000-F53C3 Functional blocks  1 million equival

12 UG034, July 1, 2014 System  PCI Express Gen 3 x8, for 128 Gb/s (2 x64 Gb/s - Rx, Tx) throughput  USB  JTAG Controller  Atmel ATmega2560

UG034, July 1, 2014 13 Chapter 2 – General Description In this chapter, you will learn the following about the ACX-BRD-HD1000-100G Development Board:

14 UG034, July 1, 2014 Use Modes This section describes the standalone and in-system (or “plug-in”) use modes for the development boar

UG034, July 1, 2014 15 PCIe Plug In CardPower Supply Figure 4: In-System Use Mode On-Board Memory The development board has the following memories ava

16 UG034, July 1, 2014  IOs  BRAM  Fabric  Take appropriate corrective action by the embedded control software. Board-Specific Design Issue

UG034, July 1, 2014 17 Chapter 3 – Development Environment Setup In this chapter, you will learn how to perform the following tasks: Installing the AC

18 UG034, July 1, 2014 Figure 5: Software Development Environment For more details on Steps 1 through 6 refer to the Achronix Software & Lice

UG034, July 1, 2014 19 Standalone Board ConnectionsUSB CableJTAG Ribbon CableDevelopment PC (Client)Bitporter PodPower SupplyDevelopment Board Figu

2 UG034, July 1, 2014 Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark an

20 UG034, July 1, 2014 In-System Board ConnectionsUSB CableJTAG Ribbon CableDevelopment PC (Client)Bitporter PodPCIe Slot ConnectionPower Supply F

UG034, July 1, 2014 21 Connect the development PC Configure the HD1000 and Run the Application There are three sources currently supported for the FP

22 UG034, July 1, 2014 CPU x8 Mode ProgrammingSPI Flash ProgrammingSD CARDJTAG Programming Figure 8: ACX-BRD-HD1000-100G Board Configuration Modes

UG034, July 1, 2014 23 HD1000 (U33) Connection BYPASS_CLR_MEM J18 SW8 HDR_BYPASS_CLR_MEM 1 CONFIG_SCRUBBING_ENABLE K19 HDR_CFG_SCR_ENABLE 2 CONFIG_SCR

24 UG034, July 1, 2014 Pin Name on HD 1000 (U33) x1 Boot from Flash (Serial Mode) - EFC CPU Mode CPU_CLK CPU CLOCK -- CONFIG_RSTN Active-low config

UG034, July 1, 2014 25 Chapter 4 – Interfaces In this chapter you will learn about the interfaces that are available on the HD1000 FPGA and also the o

26 UG034, July 1, 2014 HD1000 FPGA InterfacesBLNBLNBLNCNFGBANK EAST-CENTRE(BYTE 0-12)BANK EAST-NORTH(BYTE 0-12)BANK EAST-SOUTH(BYTE 0-12)BLNBLNBLN

UG034, July 1, 2014 27 ACX-BRD-HD1000-100G Development Board Interfaces Figure 10 shows the interfaces available on the development board. T

28 UG034, July 1, 2014 Figure 11 below shows all of these different interfaces on the development board. Figure 11: ACX-BRD-HD1000-100G Developm

UG034, July 1, 2014 29 The CFP cage is directly connected to the ten bidirectional 12.5 G SerDes lanes. These are designated SerDes Bot

UG034, July 1, 2014 3 Table of Contents Copyright Info ...

30 UG034, July 1, 2014 Signal Name SerDes No Pin on HD1000 (U33) CFP1_RX_N9 F28 CFP1_TX_P9 A28 CFP1_TX_N9 B28 SERDES_CFP1_CLK1_P M31 SERDES_CFP1_C

UG034, July 1, 2014 31 Signal Name SerDes No Pin on HD1000 (U33) Pin on Header (J1) INTERLAKEN1_CLK3_N BB31 NA INTERLAKEN_TX_P10 30 – 31 BJ41 J4 INTE

32 UG034, July 1, 2014 Signal Name SerDes No Pin on HD1000 (U33) Pin on Receptacle (J2) INTERLAKEN1_CLK1_N BB32 NA INTERLAKEN1_RX_CLK_P NA A1 INT

UG034, July 1, 2014 33 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_TRST_N D34 FMC_DP_M2C_P0 BF19 C7 FMC_DP_M2C_N0 BG19 C6 FMC_DP_M2

34 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_LA_N3 AW8 G10 FMC_LA_P4 BC7 H10 FMC_LA_N4 AW7 H11 FMC_LA_P5 BB8 D

UG034, July 1, 2014 35 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_LA_N29 BG1 G31 FMC_LA_P30 BB4 H34 FMC_LA_N30 BC3 H35 FMC_LA_P31 BC4

36 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_HA_N20 AE3 E19 FMC_HA_P21 AC4 K19 FMC_HA_N21 AF3 K20 FMC_HA_P22 A

UG034, July 1, 2014 37 Signal Name Pin on HD1000 (U33) Pin on Connector (J3) FMC_HB_N18 BJ8 J36 FMC_HB_P19 BF8 E34 FMC_HB_N19 BD8 E33 FMC_HB_P20 BK8

38 UG034, July 1, 2014 Signal Name SerDes No Pin on HD1000 (U33) Pin on PCIe x8 Finger (J4) PCIE_TXN4 C15 A30 PCIE_RXP5 5 G16 B23 PCIE_RXN5 F16 B2

UG034, July 1, 2014 39 JTAG (J11) You can use the JTAG interface for communicating with the board. This interface lets you access the JTAG

4 UG034, July 1, 2014 Chapter 3 – Development Environment Setup ... 17 Installing the ACE and Synopsys s

40 UG034, July 1, 2014 Controller Interfaces The Atmel Atmega2560 (U35) controller has the following interfaces for performing several tasks on the

UG034, July 1, 2014 41 you with an ACE template to correctly allocate these IO pins, Bank East-South (Byte 0 – 12), for your designs. Appendix A detai

42 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on MT41J128M16JT (U21) DDR3_BA1 AD1 N8 DDR3_BA2 AN2 M3 DDR3_CK AF10 J7 DDR3_CK_N AF9 K7

UG034, July 1, 2014 43 Signal Name Pin on HD1000 (U33) Pin on MT44K32M18RB (U31) (U36) RLD_DQ15 Y4 M9 RLD_DQ16 W3 M11 RLD_DQ17 AB3 N8 RLD_DQ18 AB9

44 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on MT44K32M18RB (U31) (U36) RLD_DQ65 R10 K1 RLD_DQ66 M9 L6 RLD_DQ67 M10 L4 RLD_DQ68 J

UG034, July 1, 2014 45 Signal Name Pin on HD1000 (U33) Pin on MT44K32M18RB (U31) (U36) RLD_QK1 AA3 K9 RLD_QK1_N AA4 J8 RLD_QK2 V9 D5 RLD_QK2_N V10

46 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on CY7C2565XV18 (U22) QDR2_Q7 BA40 C10 QDR2_Q8 BJ44 B11 QDR2_Q9 AW43 P9 QDR2_Q10 AW41 N

UG034, July 1, 2014 47 Signal Name Pin on HD1000 (U33) Pin on CY7C2565XV18 (U22) QDR2_D12 BG47 J9 QDR2_D11 BJ47 L9 QDR2_D10 BK47 M9 QDR2_D9 BC44 N10

48 UG034, July 1, 2014 User Interfaces Use these interfaces to configure and drive the board, connect cables, expand I/O, review statu

UG034, July 1, 2014 49 Figure 13: ACE GUI for the Bitporter Pod For more details, refer to the “ACE User Guide (UG001)” and the “Bitport

UG034, July 1, 2014 5 Chapter 6 – Atmel Microcontroller ... 55 Temperature Sensing and R

50 UG034, July 1, 2014 Signal Pin on HD1000 (U33) Connector SMA Function PAD0_CLK_BANK_SE N38 J49 PAD1_CLK_BANK_SE P37 J50 Digilent connector (J2

UG034, July 1, 2014 51 HD1000 (U33) Switch (SW7) CONFIG_CLKSEL M17 CFG_CLKSL 5, 12 PROGRAM_ENABLE0 K15 PRG_EN0 6, 11 PROGRAM_ENABLE1 M19 PRG_EN1 7, 10

52 UG034, July 1, 2014 Chapter 5 – Clocking In this chapter you will learn about the crystals and oscillators on the board. These provide the input

UG034, July 1, 2014 53 Table 20: Sample DIP Switch Settings to Generate Desired Synthesizer Output Clocks M Counter (SW12) N Counter (SW13) M/N Outpu

54 UG034, July 1, 2014 Signal Name Pin on HD1000 (U33) Pin on ICS853310 (U72) INTERLAKEN1_CLK2_P AY32 20 INTERLAKEN1_CLK2_N AW32 19 INTERLAKEN1_

UG034, July 1, 2014 55 Chapter 6 – Atmel Microcontroller You can use the on-board, Atmel Atmega2560 microcontroller (MCU) for monitoring an

56 UG034, July 1, 2014  Configuring the HD1000 through Serial or CPU mode  Responding to over-temperature/over-current alarm  Driving status

UG034, July 1, 2014 57 Appendix A – HD1000 Pins and their connections to the SO-DIMM Socket Table 25: ACX-BRD-HD1000-100G SO-DIMM Socket Pins and thei

58 UG034, July 1, 2014 Category Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) SODIMM_DQ31 M48 70 SODIMM_DM3 L49 63 SODIMM_DQS3 P49 6

UG034, July 1, 2014 59 Category Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) (Byte 5) SODIMM_CSN1 K47 121 SODIMM_CKE0 M47 73 SODIMM_CK

6 UG034, July 1, 2014 List of Figures Figure 1: ACE Development Environment...

60 UG034, July 1, 2014 Category Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) VDD_17 123 VDD_18 124 Reference Voltages VTT_1 203

UG034, July 1, 2014 61 Category Signal Name Pin on HD1000 (U33) Pin on SO-DIMM Socket (J41) VSS_45 178 VSS_46 179 VSS_47 184 VSS_48 185 VSS_49 1

62 UG034, July 1, 2014 Appendix B – LEDs, Buttons, Jumpers, and Switches The following tables list the various LEDs, buttons, jumpers, and switches

UG034, July 1, 2014 63 Jumpers Table 28: Jumpers and their Functions Jumper Implementation Connected Pins Function JTAG J54 Surface Mount Resisto

64 UG034, July 1, 2014 Jumper Implementation Connected Pins Function 1 & 2 Connects QDRII_TMS J27 4-Pin Jumper None 1 & 2 Selects QD

UG034, July 1, 2014 65 Jumper Implementation Connected Pins Function 1 & 2 Selects VREF_A_M2C for pin AE15 (U33) 2 & 3 Selects ADJ _FMC

66 UG034, July 1, 2014 Jumper Implementation Connected Pins Function J46 Surface Mount Resistor 1 Selects VDDL_REG 0.75V-1.2V 2 0.75V 3 1.0V

UG034, July 1, 2014 67 Switch Function Connection No Position Through Pin Signal SW14 1 Clock select input 31 E_SEL1_2 2 Clock select input 30 E_SEL0_

68 UG034, July 1, 2014 Appendix C – Troubleshooting Q: Where can I find more information about this kit and the HD1000? A: Visit the Achronix

UG034, July 1, 2014 69 Appendix D – Revision History The following table lists the revision history of this document. Date Version Revisions 04/05/201

UG034, July 1, 2014 7 List of Tables Table 1: ACX-BRD-HD1000-100G Board Configuration Mode (J31) ... 2

8 UG034, July 1, 2014 Preface About this Guide The Achronix ACX-KIT-HD1000-100G Development Kit for the AC22IHD1000-F53C3 FPGA, delivers a practi

UG034, July 1, 2014 9 Reference Documents Speedster22i FPGA Family Datasheet (DS004) ACE User Guide (UG001) Achronix Software & License User Guide