UG035 (v1.0), March 19, 2012 1LaneLinxTM User Guide UG035 (v1.0) – March 19, 2012
2 UG035 (v1.0), March 19, 2012 Table of Contents Introduction ...
UG035 (v1.0), March 19, 2012 3Introduction LaneLinxTM is a lightweight, multi-gigabit per second serial protocol. It enables high bandwidth, serial co
4 UG035 (v1.0), March 19, 2012 Figure 1 – LaneLinx Block diagram
UG035 (v1.0), March 19, 2012 5XG_Lanelinx Details LaneLinx2p5g: This block is the instantiation of the Hard SerDes IP contained within the Speedster
6 UG035 (v1.0), March 19, 2012 The signals • lane0_o_pma_txready and • lane0_o_pma_rxready are OR’ed together to create a signal called “lane_
UG035 (v1.0), March 19, 2012 7 The Link_Training block This block generates the training signal for linking up the channel at the required data-rate.
8 UG035 (v1.0), March 19, 2012 XG_Lanelinx Pin Description Signal Description ref_clk_p Input. Reference clock p-side (Differential clock-pin) ref
UG035 (v1.0), March 19, 2012 9Reference Design The Reference Design consists of two blocks, TX_data_gen and RX_data_comp. 1. TX_data_gen: This block
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