Achronix Speedster22i Configuration Uživatelský manuál stáhnout pdf (Strana 7)

UG033, December 18, 2013

The startup sequence consists of sequentially asserting a number of signals to ensure proper

operation during user mode. These events are highlighted in Table 2 below.

Table 2: Startup Sequence Events

Stage

Event

Assert Global Clock Enable

Assert I/O Enable

Assert Global Reset Enable

Assert Global Core Enable

Assert Config Done

Assert User Mode Enable

The shutdown sequence is very similar in nature to the startup sequence and essentially

entails deasserting these same signals in reverse order.

User Mode: Once the device enters user mode, the design has been fully programmed

and the user can start sending and receiving data to/from the FPGA and performing intended

operations.

1 2 3 4 5 6 7 8 9 10 11 12 ... 19 20

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Achronix Speedster22i Configuration Uživatelský manuál Strana 7