Achronix Speedster22i Configuration Uživatelský manuál stáhnout pdf (Strana 19)

UG033, December 18, 2013

3. Lower VCCFHV_EFUSE[3:1], VCCRAM_EFUSE[3:1] and VDDA_NOM_E/W all back

down to 1.0V. Run phase 3 steps to validate the eFuse blowing process and return the

FCU back to a state to resume programming operations.

Once the eFuses are blown, the Speedster22iHD FPGA will be ready to accept encrypted

bitstreams as part of regular programming operation.

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Achronix Speedster22i Configuration Uživatelský manuál Strana 19