Achronix ACE Version 5.0 Uživatelský manuál Strana 361
- Strana / 389
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
run gate balance Chapter 5. Tcl Command Reference
[-fanout limit clone
<arg>]
Optional Apply fanout cloning on nets
with fanout greater than this
limit
run final drc checks
run final drc checks [-reportsdir <arg>] [-debugdir <arg>]
This command performs final DRC checks on the design.
Argument Required/Optional Description
[-reportsdir <arg>] Optional Reports directory name
[-debugdir <arg>] Optional The optional -debugdir <dir>
option is used to override the
default location for debug files
during this step.
run fpga download
run fpga download [-outputdir <arg>] [-debugdir <arg>] [-download connection
<arg>] [-download pod names <arg>] [-jam file <arg>]
This command dowloads the generated bitstream to the target device.
Argument Required/Optional Description
[-outputdir <arg>] Optional Output directory name
[-debugdir <arg>] Optional The optional -debugdir <dir>
option is used to override the
default location for debug files
during this step.
[-download connection
<arg>]
Optional Bitporter connection type
(single, multiple)
[-download pod names
<arg>]
Optional Comma-separated list of
bitporter pod names. Used if
download connection is
”multiple”
[-jam file <arg>] Optional Optional jam (STAPL) file to
download. The default jam file
in your output directory will be
used if this is not specified
run gate balance
run gate balance
This command generates extra gate delays for reconvergent (skewed) paths as specified by the user directive
set extra delay.
349 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012
- ACE User Guide 1
- Copyright Info 2
- Contents 3
- About This Guide 13
- Related Documents 13
- Getting Started 14
- ACE Quickstart Tutorial 15
- Concepts 16
- Text Editor 18
- HTML Report Browser 19
- Basic PLL Configuration Editor 32
- BRAM Configuration Editor 35
- DDR3 Configuration Editor 40
- Ethernet Configuration Editor 51
- FIFO Configuration Editor 55
- Interrupt Settings Page 72
- LRAM Configuration Editor 78
- LRAM FIFO Configuration Editor 81
- Memory Map Page 88
- ROM Configuration Editor 97
- SerDes Configuration Editor 100
- Editors Chapter 3. Concepts 102
- Channel Bonding Page 118
- VCD Waveform Editor 126
- Fast views 129
- Projects View 130
- Flow View 132
- Options View 134
- Multiprocess View 141
- Tcl Console View 147
- Search View 148
- Selection View 152
- Views Chapter 3. Concepts 155
- Figure 3.74: Selection View 155
- Critical Paths View 156
- Critical Path Diagram View 160
- Package View 164
- IO Assignment View 168
- Clock Regions View 172
- Netlist Browser View 174
- Placement Regions View 177
- Outline View 180
- IP Libraries View 181
- IP Diagram View 182
- IP Problems View 184
- Download View 186
- ”net192.168.100.101” 187
- Create Project Dialog 188
- Load Project Dialog 189
- Create Implementation Dialog 190
- Restore Implementation Dialog 191
- Save Implementation Dialog 192
- Create a New Text File Dialog 194
- Add Source Files Dialog 195
- Save Placement Dialog 197
- Save Script File Dialog 199
- New IP Configuration Dialog 200
- Configure Selected IOs Dialog 203
- Configure Table Columns Dialog 207
- Search Filter Builder Dialog 211
- Save Placement Regions Dialog 215
- Toolbars 216
- Preferences 217
- Floorplanner view 220
- IP Diagram Preference Page 225
- Package View Preference Page 230
- Text Editors Preference Page 234
- Projects 237
- Project File 239
- Source Files 239
- IP Configurations 239
- Output Files 240
- Log Files 240
- Flow Steps 242
- Flow Status 242
- Clock Report 243
- Utilization Report 243
- Pin Assignment Report 243
- Timing Report 244
- I/O Timing Report 245
- Routing Report 245
- Power Dissipation Report 245
- Multiprocess Summary Report 245
- Advanced Concepts 247
- Running ACE 248
- Working With Perspectives 249
- Opening Views 250
- Moving and Docking Views 250
- Rearranging Tabbed Views 250
- Creating Fast Views 251
- Tiling Editors 251
- Maximizing a View or Editor 251
- Creating Projects 252
- Loading Projects 252
- Removing Projects 252
- Saving Projects 252
- Adding Source Files 254
- Removing Source Files 255
- Creating Implementations 255
- Saving Implementations 256
- Restoring Implementations 256
- Copying Implementations 257
- Removing Implementations 257
- Running the Flow 259
- Place and Route Steps 260
- Design Completion Steps 260
- FPGA Programming Steps 261
- 2 5035008 263
- Using the Tcl Console 267
- Command Help 268
- Text Limit 269
- Clearing the Console 269
- Viewing the ACE Log File 270
- Object Type Prefixes 270
- Creating an IP Configuration 271
- Setting the IP Configuration 272
- Viewing the Floorplanner 273
- Selecting Objects 274
- Deselecting Objects 274
- Toggling Mouse Tools 275
- Filtering the View 275
- Getting Object Tooltips 275
- Viewing Object Labels 276
- Viewing the Package Layout 277
- Pre-Placing a Design 281
- Removing Placement 283
- Analyzing Critical Paths 284
- Zooming to Critical Paths 286
- Using Critical Path Diagrams 286
- Intermediate Nodes 290
- Managing I/Os 294
- Running the SnapShot Debugger 295
- Using the SnapShot Macro 297
- VHDL Instantiation: 300
- Setting Up the Scan Chain 302
- Entering a Trigger Pattern 302
- Configuring Test Stimulus 303
- Setting Triggering Range 304
- Configuring the Samples 304
- Collecting Samples 304
- Batch Mode 305
- Playing a STAPL File 306
- Optimizing a Design 307
- Placement Region Preferences 309
- Deleting Placement Regions 313
- Tcl Command Reference 314
- Usage Notes: 349
- Revision History 385
- Version 4.2.0: 387
- Version 3.2.0: 388
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