Achronix Speedster22i sBus Uživatelský manuál stáhnout pdf (Strana 5)

UG047, October 24, 2013

List of Figures

Figure 1: The HD1000 FPGA with sBus interfaces ................................................................................... 9

Figure 2: The sBus interface signals ......................................................................................................... 10

Figure 3: 32-bit Data Width sBus Read Operation ................................................................................... 12

Figure 4: 8-bit Data Width sBus Read Operation ..................................................................................... 12

Figure 5: 32-bit Data Width sBus Write Operation .................................................................................. 13

Figure 6: 8-bit Data Width sBus Write Operation .................................................................................... 14

Figure 7: Single Master for a single sBus Slave ....................................................................................... 15

Figure 8: Single Master for two sBus Slaves ............................................................................................ 16

Figure 9: sBus Slave Interface .................................................................................................................. 16

Figure 10: sBus Master Block Diagram.................................................................................................... 20

Figure 11: sBus Master State Machine ..................................................................................................... 21

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Achronix Speedster22i sBus Uživatelský manuál Strana 5