Achronix Speedster22i sBus Uživatelský manuál stáhnout pdf (Strana 12)

12 UG047, October 24, 2013

6. Assert the o_sbus_ack signal, when data is ready.

7. Transmit the serial data on the o_sbus_data[1:0] signals using the ordering [D1:D0]…

[D31:D30] in 16 cycles.

8. De-assert the o_sbus_ack signal after 16 cycles, when the transmission is complete.

Figure 3 shows the timing diagram for a 32-bit data width, sBus read operation.

Figure 3: 32-bit Data Width sBus Read Operation

8-bit Data-width Mode

For an 8-bit data-width mode read operation, you must do the following.

1. Assert the i_sbus_req signal for 9 cycles.

2. De-assert i_sbus_data[0] during the first cycle.

3. Send the LSB of the 17-bit long read address on i_sbus_data[1] during the first cycle.

4. Send the remaining 16 bits of the read address on i_sbus_data[1:0] in the following order

[A2:A1]…[A16:A15] over the next 8 cycles.

5. De-assert i_sbus_req signal.

The sBus slave will decode the read operation and respond as follows.

6. Assert the o_sbus_ack signal, when data is ready.

7. Transmit the serial data on the o_sbus_data[1:0] signals using the ordering [D1:D0]…

[D7:D6] in 4 cycles.

8. De-assert the o_sbus_ack signal after 4 cycles, when the transmission is complete.

Figure 4 shows the timing diagram for an 8-bit data width, sBus read operation.

Figure 4: 8-bit Data Width sBus Read Operation

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 26 27

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Achronix Speedster22i sBus Uživatelský manuál Strana 12