Achronix Speedster22i DDR Uživatelský manuál stáhnout pdf (Strana 30)

Memory Interface Latency

Depending on the data rate and the mode (width) used, the write and read latency for the

DDR3 controller will vary. Table 4 below provides detailed clock cycle counts for write and

read latencies for each of these cases.

Mode Data-Rate

Write-Latency

(Clock Cycles)

Read-Latency

(Clock Cycles)

Up to 1066 Mbps

Up to 1600 Mbps

From 1601 Mbps to 1866 Mbps

Wide-Bus

Up to 1600 Mbps

Wide-Bus

From 1601 Mbps to 1866 Mbps

Table-4: Latency Information for different memory controller modes

30 UG031, Nov 18, 2014

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Achronix Speedster22i DDR Uživatelský manuál Strana 30