Achronix Speedster22i 10G/40G/100G Ethernet Uživatelský manuál Strana 7
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Hodnocené. / 5. Na základě hodnocení zákazníků
UG029, September 6, 2013
7
Table of Figures
Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram ...................................................... 10
Figure 2: Interface Signal List .................................................................................................. 12
Figure 3: 10/40/100G Ethernet MAC IP Wizard ....................................................................... 22
Figure 4: Generate IP Design Files dialog box ........................................................................ 23
Figure 5: Simulation Flow ........................................................................................................ 25
Figure 6: System clock distribution for the 20-Bit SerDes interface ......................................... 26
Figure 7: Example implementation for the FIFO clock and reset multiplexers ......................... 27
Figure 8: Transmit FIFO Interface Block Diagram ................................................................... 30
Figure 9: Receive FIFO Interface Block Diagram .................................................................... 31
Figure 10: Credit based application interface .......................................................................... 32
Figure 11: FIFO Transmit Interface – Single Frame Transfer .................................................. 37
Figure 12: FIFO Transmit Interface – Frame Transfer with User Application Pause ............... 38
Figure 13: FIFO Transmit Interface – Back-to-Back Frame Transfer ....................................... 38
Figure 14: FIFO Transmit Interface – Frame Transfer with Error ............................................. 38
Figure 15: FIFO Receive Interface – Single Frame Transfer ................................................... 40
Figure 16: FIFO Receive Interface – Frame Transfer with data valid signal not continuously
high .................................................................................................................................... 40
Figure 17: FIFO Receive Interface – Frame Transfer with Error .............................................. 41
Figure 18: FIFO Receive Interface – Frame Transfer with User Pause ................................... 42
Figure 19: FIFO Sections Configuration and Signals ............................................................... 44
Figure 20: FIFO Sections Related Signaling ............................................................................ 44
Figure 21: Read in 32-bit Data Bus Mode................................................................................ 50
Figure 22: Read in 8-bit Data Bus Mode.................................................................................. 50
Figure 23: Write in 32-bit Data Bus Mode ................................................................................ 50
Figure 24: Write in 8-bit Data Bus Mode .................................................................................. 50
Figure 25: Power State Transitioning Diagram ........................................................................ 53
Figure 26: Auto negotiation Use Flow ...................................................................................... 55
- Speedster22i 10/40/100 1
- Gigabit Ethernet User Guide 1
- Copyright Info 2
- Table of Contents 3
- Table of Figures 7
- Overview 8
- Functional Description 10
- Interface Signal List 12
- Global Signals 13
- Receive FIFO Interface 13
- Transmit FIFO Interface 15
- PMA TX/RX Interface 16
- Signal Name 17
- Serial Bus Interface 18
- SerDes (off-chip) Interface 19
- Transmitted Frame Status 19
- Timestamp Timer 19
- MAC/PCS Status Indications 20
- Implementation with ACE 21
- Simulation 24
- .vp or .ve file extenstion 25
- .vma file extenstion 25
- Clock Distribution 26
- Reset Considerations 28
- Fabric FIFO Interface 29
- Credit Handling 32
- Data Structure 33
- Valid Bytes 34
- Byte Number 36
- Frame Status 42
- FIFO Thresholds 43
- FIFO nearly full 44
- FIFO has at least 44
- FIFO is full 44
- Flow Control Interface 45
- Transmit Pause/PFC Operation 47
- Receive Pause/PFC Operation 47
- Write Operation 50
- PMA Management Interface 51
- Power State Sequencing 53
- Auto-Negotiation 54
- Function 55
- Related 55
- Registers 55
- IEEE 1588 Timestamping 58
- Channelized MAC Registers 61
- Transmitted 64
- Bit Name 70
- 1000Base-X / SGMII PCS 71
- Global Registers 77
- Channelized PCS Registers 79
- Auto-Negotiation Registers 87
- PMA Registers 93
- 1A[7:4] 95
- 1B[3:0] 95
- 1B[6:4] 95
- 1C[7:3] 95
- +1 is 4’h9 96
- 51[3:2] 97
- 53[2:2] 97
- 53[3:3] 97
- 8[6:6] 99
- 21[5:1] 99
- 23[5:1] 99
- 25[2:0] 99
- UG029, September 6, 2013 101
- Statistics Data Registers 102
- Receive Statistics Vector 103
- Description 104
- Transmit Statistics Vector 105
- References 107
- Revision History 108
Související produkty a manuály pro Počítačový hardware Achronix Speedster22i 10G/40G/100G Ethernet
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